Some Bearish Thoughts on RISC-V

I have been a supporter, if not an outright cheerleader, of RISC-V, the open source instruction set architecture (ISA). In my writings here on Interconnected and elsewhere, I’ve often used RISC-V as an example of technological innovation, broadly, and an antidote to countries seeking self-reliance in semiconductor technology, specifically. Indeed, RISC-V has become an increasingly prominent piece of the industrial policies in China, India, and Pakistan to name just a few countries.

While I still firmly believe in RISC-V’s long-term potential, how valuable or pivotal it really is in helping a country achieve self-reliance is rather questionable. So time to update my own thinking with a more bearish, sobering, and less cheerlead-y take on RISC-V.

Weak Software Ecosystem

RISC-V isn’t the first open source ISA. Previously projects, like OpenRISC and OpenSPARC, have all fallen out of relevance largely because there was no software ecosystem to support their growth.

RISC-V is facing the same predicament.

Herein lies an important observation: as core as an ISA may be in the entire semiconductor production chain, it’s too small a piece of the puzzle to make a big difference alone. Borrowing an analogy from an entrepreneur friend: an open source ISA is more like the English grammar -- it’s free and open to anyone but inherently not that valuable. What’s valuable is the great novels, research, legal contracts, business negotiations, etc. done using English that’s valuable. And for that to happen, you need enough people to read, write, and speak English.

Similarly, the production silicons (actual chips that can be deployed in devices, the “novels” of the ecosystem) is what will make RISC-V valuable, not its nature of being an open source ISA. Sadly, RISC-V isn’t at that level yet, because not enough developers “speak” RISC-V. Thus, it’s not surprising that there is no volume production of RISC-V-based chips, despite the enthusiasm and promise surrounding the technology.

To be sure, the RISC-V International foundation is working hard to foster that ecosystem. More compilers (the software layer that translates code, like C, into machine instructions for a chip to execute) are also being supported -- a critical software layer necessary to draw more developers into the project. But building a developer ecosystem that spans both hardware and software is a difficult undertaking -- a long-haul that’s a constant chicken-or-egg exercise. And even if a sustainable ecosystem is achieved, that’s just the first of many steps to justify to the market that producing RISC-V silicons at scale is worthwhile. RISC-V is still in the early days of that long journey.

Technical Raison d'être

All the geopolitical tension has shoved RISC-V into the limelight, so much so that we forget its technical raison d'être, which is important to know, ironically, in order to put RISC-V in its proper role in the current geopolitical context.

One of the core purposes of RISC-V is to push innovation in a new way as Moore’s Law reaches its limit. Moore’s Law, put simply, is the observation that the number of transistors you can fit on a chip doubles every two years. As that doubling reaches its limit (everything has a limit), the next big challenge is: what functionalities can we still squeeze out of this form factor to keep innovation going until the next paradigm, i.e. quantum computing, matures.

RISC-V lets chip designers do that “squeezing” and customizing by being simple (or reduced, as in the “R” in RISC) and free (because it’s open source, thus no licensing fees or constraints). This “free simplicity” is crucial, because it enables quick and economical experimentation to make custom-purpose chips that can squeeze in specific functionalities, while stripping away unnecessary ones (which you’d often find in general-purpose chips). For example, a security camera that needs to do facial recognition only needs a chip that can process computer vision models well, i.e. lots of matrix multiplication, and send an alert if it detects a problem -- nothing else. Because of this ability to customize, chips designed the RISC-V way also tend to consume less power.

Thus, RISC-V’s technical motivation fills an important purpose in the larger semiconductor ecosystem, but can’t (and shouldn’t be expected to) replace the general-purpose ISAs, Intel’s x86 and Arm.

The possibility of ISAs being sanctioned is also quite remote. Even with the pending Nvidia-Arm acquisition, which will make both dominant ISAs “American” soon, the ISA part is too small on a macro-level and isn’t a real bottleneck of advancement. Sanctioning ISAs just to keep China down, especially given Intel’s poor shape, may do more harm than good to American industries. The Semiconductor Industry Association, the industry’s lobbying arm in DC, has already criticized previous rounds of sanctions on Huawei.

The real chokeholds are: 1. EDA software suites to design chips based on a given ISA, most of which are proprietary software; 2. Advanced lithography equipment that can take those designs and etch them onto the smallest chip Moore’s Law would allow, most of which are provided by only a handful of vendors worldwide, like ASML and Applied Materials. These two parts are also easier to sanction from an execution standpoint than ISA intellectual properties. (See my previous post on how another RISC-based ISA, MIPS, ended up in China via offshore entities and a bankruptcy.)

Are Nvidia+Arm, AMD+Xilinx Catalysts?

All my bearish, critical thoughts aside, RISC-V actually has a historical opportunity in front of it. The industry is going through a massive consolidation phase, and two big players, Arm and Xilinx, are being acquired by Nvidia and AMD, respectively.

Arm is the RISC-based ISA that has basically monopolized the mobile industry, and Nvidia is one of its many customers. With Nvidia owning Arm, all of Arm’s other customers, many of whom compete with Nvidia, will have to consider other options. RISC-V is the obvious, if not the only, alternative. Xilinx is a leading provider of FPGAs (Field Programmable Gate Arrays), which are programmable chips that have similar flexibility characteristics as RISC-V chips (so some competition here too), but are more expensive and power-consuming. They are used in high-end equipment, such as satellites and some 5G base stations. FPGA and RISC-V cores can also exist on the same system-on-a-chip (SoC), like this PolarFire SoC from Microchip:

The lane that the Nvidia-Arm deal opens up for RISC-V is plain as day. And I’m not the first, nor will be the last, to prognosticate about this opening. Whether the AMD-Xilinx deal will also be an opening is too early to tell. The impact of both deals, at large, will take years to play out.

But one thing is certain: if you are looking for a neutral source of IP that doesn’t have any potential conflict of interest, a “Switzerland”, RISC-V might be your only bet. (Not to mention, the RISC-V International foundation is literally registered in Switzerland.)

The question now is: can RISC-V seize this moment and avoid the fate of the other open source ISAs that came before it?

If you like what you've read, please SUBSCRIBE to the Interconnected email list. To read all previous posts, please check out the Archive section. New content will be delivered to your inbox (twice per week). Follow and interact with me on: Twitter, LinkedIn.